Facing the Multi-Core Fear Factor

Thomas Sterling

Center for Computation and Technology

Louisiana State University

Center for Advanced Computing Research

California Institute of Technology

Computer Science and Mathematics Division

Oak Ridge National Laboratory

Abstract

The continuing opportunity presented by semiconductor technology trends characterized as Moore’s Law also imposes significant challenges to processor, system, and software designers. The point of diminishing returns has been reached in the exploitation of logic complexity in processor design and this combined with severed problems related to power consumption has forced the industry to the strategy of integrated multiple processor cores on a single die. This “multi-core” methodology is a dramatic change from prior conventional practices and demands for the first time that the mainstream software community embrace parallel processing that was at one time reserved for the rarefied field of supercomputing. But as the scientific and technical computing arena has for a long time relied on commodity components as a mainstay of their very large systems, they too must address the new challenges of the multi-core era. With the aggravation of the memory wall and the increased dependency on application parallelism, effective use of multi-core technology for high performance computing is threatened by the complacency of backwards looking conventional practices. This talk will present a new strategy for exploiting Moore’s law and the important trend to multi-core through changes in hardware structures and software programming models. Although a departure from ordinary methods, the move to message-driven split-transaction computing augmented with memory accelerators can be non-disruptive and provide a clean sustainable approach to future computer system architectures for the next decade and a half to nano-scale technology.